A finished gate structure (such as a finished gate or transistor gate) is the transistor terminal that modulates channel conductivity. Two principle approaches for forming high-k metal gate CMOS semiconductor device gate structures are the gate-first and gate-last process approaches.
FIG. 1 depicts a conventional gate structure having a substrate 10, an oxide layer 20 and a polysilicon layer 30. Substrate 10 includes a source 40 and a drain 50. FIG. 2 depicts a Gate-last High K metal gate which includes a substrate 110, an interfacial layer 120, a high dielectric constant (High K) layer 125, and metal gate 130. Substrate 110 also includes a source 140 and a drain 150.
During the formation of such gate structures, a titanium nitride (TiN) cap may be applied between the high K layer and the metal gate. An amorphous silicon cap may be applied to the TiN cap followed by a post cap reliability anneal and an amorphous silicon cap strip. The strip of the Si cap may result in an increase in TiN surface roughness and to portions thereof being lost, thereby leading to metal work function shift and a degradation in gate stack reliability.
Accordingly, a need exists for improved systems and methods for forming semiconductor device gate structures.